LMS Laser-Modified Substrates | Caporus Technologies

The Challenge

RF Performance Is Substrate-Limited

In silicon-on-insulator (SOI) wafers, fixed charge in the buried oxide creates a parasitic conduction layer at the silicon interface. RF signals couple through it, which causes 2nd and 3rd harmonic distortion (H2/H3). Effective substrate resistivity can collapse from kΩ·cm to tens of Ω·cm.

The result is failed harmonic specs and coexistence issues in 5G front-ends.

Where Today’s Trap-Rich Layers Fall Short

Limited thermal budget. Poly-Si recrystallizes during high-temperature steps.
No spatial selectivity. The whole wafer is treated uniformly, which limits co-integration.
Degradation above about 100 °C. Trap effectiveness drops at elevated temperature.
Process incompatibility with GaN on Si and other advanced substrates.
Requires high-resistivity silicon beneath the poly-Si layer.

Diagram of the laser modification process forming a trap-dense layer beneath the surface

How It Works

Laser Modification of Silicon

A patent-pending, direct-write laser process forms embedded porosity in place, beneath the surface of the wafer.

The top layer is transparent to the laser. The silicon beneath absorbs the energy.
Rapid, localized heating and cooling with a spot size of about 10 to 50 µm.
Sub-surface cavities form without ablating or texturing the surface.
No contamination. No implanted species or deposited materials.
Surface stays planar and ready for bonding and lithography.
Fast, low-energy, and spatially selective.

What It Produces

Thermally Stable, Directly Writable, Scalable

Sealed cavities form up to several microns below a continuous, intact surface. They can be written region by region or across entire wafers.

Top-down image of laser-formed porosity after a 1200 degree C soak — **Stable after 1200 °C**Cavity morphology remains stable after a 1-hour, 1200 °C soak.

Wafer with a laser-written Caporus pattern — **Direct-write patterning**Laser-modified regions written directly, from about 10 µm features to full wafers.

200 mm wafer with laser-modified regions — **Demonstrated at 200 mm**Scaling demonstrated on 200 mm wafers, with a path to 300 mm.

Proven Results

Measured Performance

Laser-modified regions compared with unmodified control regions on the same substrate. RF testing of laser-modified wafers showed lower RF loss, higher effective resistivity, reduced H2/H3 harmonics, and reduced coupling and crosstalk, comparable to industry-standard high-resistivity trap-rich SOI at room temperature.

>40 dBm

Reduction in 2nd harmonic (H2) vs. baseline

<0.22

dB/mm insertion loss

10 kΩ·cm

High effective resistivity

1200 °C

Stable cavities after a 1-hour soak, with no blistering or warpage

10 µm

Direct-write regions from about 10 µm up to full wafers

200 mm

Demonstrated on 200 mm wafers, scalable to 300 mm

Independent third-party measurement. RF measurements were performed by Incize, an independent test laboratory.

Substrate Platforms

Compatible Substrate Platforms

LMS™ technology is designed for layered and bonded wafer architectures.

Silicon on Insulator (SOI)RF-SOI front-ends and RF + CMOS co-integration

Piezoelectric on Insulator (POI)RF acoustic filters (SAW/BAW)

GaN on SiliconCompatible with epitaxial and bonded wafers

Other Advanced SubstratesDiamond on Si, SiC on Si, and other layered and bonded architectures

Differentiation

A Simpler Path to Localized RF Substrates

LMS™ targets the RF linearity and loss of commercial trap-rich substrates, and adds the thermal budget and spatial selectivity that poly-Si cannot offer.

Compared with Poly-Si Trap-Rich Layers

	Poly-Si Trap-Rich	Caporus LMS™
RF linearity and H2/H3 suppression	Yes	Yes
Low loss, high effective resistivity	Yes	Yes
Thermal budget	Limited (recrystallization)	Stable cavities to 1200 °C
Spatial selectivity	None	Directly writable
Operating temperature	About 100 °C	125 °C and above
Substrate architecture compatibility	Limited	Broader
Ion implantation or deposition needed	Deposition (CVD poly-Si)	None

Compared with Other Localized Trap Technologies

Technology	Ion Implant	P-N Junctions	Spatially Localizable	Thermal Budget	Oxide Planarity	Integration Complexity
Implantation-based defects and cavities	Yes	No	Yes	Limited	Preserved	High
Buried P-N junctions	Yes	Yes	Yes	Good	Preserved	High
Porous Si (electrochemical etch)	No	No	Limited	Limited	Often degraded	High
Caporus LMS™	No	No	Yes	High	Preserved	Lower

Applications

Where LMS™ Technology Creates Value

Starting with RF-SOI front-ends, with applications across advanced substrate platforms.

RF Front-Ends

Antenna switches, tuners, and LNAs for 5G, 5G-Advanced, and Wi-Fi 6E/7

Heterogeneous Integration

RF next to digital or photonic devices on one wafer, and chiplets

Silicon Photonics

RF-optimized regions for low-loss, co-packaged optics

Detectors and Quantum

Monolithic active pixel sensors (MAPS) and quantum devices

Partner With Caporus

Evaluate LMS™ Wafers on Your Platform

We are engaging partners on RF-SOI integration, GaN on Si, POI, heterogeneous integration, detectors, quantum, and new applications.

Joint evaluation. LMS™ wafers benchmarked in your flow, on your substrate.
Co-development of head-to-head data against commercial trap-rich substrates.
Drop-in process. The planar, bond-ready surface fits standard ion-slicing and bond-and-etch-back flows.
Licensing pathways for wafer manufacturers.

Let’s Talk About Your Substrate Requirements

Share your platform and targets, and we will set up an evaluation against a shared benchmarking plan.

Contact Us

LMS™ Laser-Modified Substrates